1. Field of the Invention
This invention relates to high performance computing network systems, and more particularly, to clock and data recovery methods for systems using serialized data transmission.
2. Description of the Relevant Art
The performance of computing systems is dependent on both hardware and software. In order to increase the throughput of computing systems, the parallelization of tasks is utilized as much as possible. To this end, compilers may extract parallelized tasks from program code and hardware may include multiple copies of structures to execute the parallelized tasks. The structures may include functional units, processor cores, and nodes.
Communication between the multiple structures may utilize wide communication buses, i.e., buses that transport data words of 16-bits, 32-bits, 64-bits, or more in parallel. The physical implementation of such communication buses may consume significant area on an integrated circuit or system. Additionally, cross-capacitance, electromigration interference (EMI), and parasitic inductance on wide buses increase the power consumption and noise effects of the computing system. Such parasitic effects may become more pronounced with increased operational frequencies and reduced geometric dimensions of the wide buses themselves, bond wires, integrated circuit (IC) package leads, and external supply lines. Mismatch of impedance values at the end of transmission lines may result in reflection or ringing, increased propagation delays, and voltage droop of the signals being transmitted.
Reducing the problems with high-speed parallel data transmission may include serializing the parallel data at the transmission side before transmission and then de-serializing the transmitted data on the receiver side upon reception. A pair of Serializer and Deserializer (SERDES) circuits may be used for this purpose.
One way of further reducing communication lines and the associated issues is by eliminating a dedicated clock between individual SERDES circuits. If the individual SERDES circuits are the same circuit board, they may share a clock source and therefore may not require a clock signal from one SERDES circuit to the other. However, if the SERDES circuits are far apart on the circuit board or are not on the same board, then a method for transmitting a clock signal from the transmitting circuit to the receiving circuit is required. One method for transmitting a clock signal is to embed the clock signal within the data stream.
Recovering an embedded clock may present difficulties. Data may be encoded such that a minimum number of data state transitions occur for a given number of bits transmitted. The receiving unit may require an accurate clock to begin with and this clock source may need to be capable of fine tune adjustments in order to match the transmitting circuit's clock if data rates above a gigabit per second (Gbit/s) are to be reliably achieved.
Another challenge may arise from intentional variations of the transmitting circuit's data clock. A data clock may be modulated within a known range in a method known as Spread Spectrum Clocking (SSC). SSC may be utilized to prevent EMI emissions in a single frequency spectrum. By gradually moving the transmitter frequency between two set frequencies, EMI emissions are spread across a wider frequency spectrum such that no single frequency is impacted for long. While SSC has benefits of reducing EMI noise, it may create a challenge for recovering the data clock.